The driving force for the development of new packaging solutions is the development of new electronic devices. Such devices support the pervasive application of information technology including transmitters and receivers, wireless chip sets, high speed modems, microprocessors, memory, automobile, and aircraft avionics to mention a few that all enhance the lives of our society.
Traditional packaging technology has supported device protection and performance requirements have involved such substrates as dual in-line packaging (DIP) and quad flat package (QFP). In the vast majority of applications of this technology, a semiconductor chip is electrically connected to the package by wire bonding. The DIP uses pins to connect the packaged chip to the electronic system and these pins are inserted into a print circuit board or socket during assembly. The leads of the QFP are solder mounted on a surface of the printer circuit board rather than being inserted into the board as is the case with DIP. This surface mount technology (SMT) can support many more package to board leads than DIP in a much smaller “footprint” on the board. At about 250 leads, however, the increasing difficulty in manufacturing the QFP format has tended to establish a practical limit to its further extension to higher lead count. Accordingly, the industry has moved away from QFP to ball grid array format to support higher lead count.
FIG. 1 illustrates one embodiment of a prior art ball grid array which includes a semiconductor chip 12 that is attached to a carrier substrate 14, such as a laminate, by way of an adhesive 16. Wire bonds 18 are connected to bond pads (not shown) on the surface of a semiconductor chip 12 down to bond pads (not shown) on the carrier substrate 14. A first set of solder bump connectors 20 are provided on the underside of the carrier substrate which are typically used to attach the ball grid array to a print circuit board. An encapsulation layer 22 is also provided. FIG. 2 illustrates another embodiment of a ball grid array assembly 10, which also includes a chip semiconductor device 12 that is attached to the carrier substrate 14. However, in this embodiment, the semiconductor chip 12 is attached by a second set of semiconductor solder bumps 24 to bond pads on the upper surface of the carrier substrate 14. This embodiment also includes the first set of solder bump 20 connections on the underside of the carrier substrate 14 used to connect the ball grid array to a printer circuit board. This embodiment also may include an encapsulation 22 to protect the semiconductor device 12 and its electrical connections 24.
As the number of transistors in a chip increases, so must the number of chip bond pads needed to support them with power ground, clock and signal. Thus, as chip complexity increase, the practical limit for peripheral chip pads tend to be exceeded. Wire bonding technology has been extremely successful in supplying the chip-to-substrate interconnect at an affordable cost. However, peripheral wire bonding is limited in its pad count to about 900 pads on the chip. About 900 pads, the production problems associated with wire bonding begin to affect production throughput as well as yield. Ultimately, these problems equate to increased cost. Wire bonding is more applicable to peripherally bonded chips. With peripheral input/output connections, the voltage drop along the chips power and ground lines will impact the signal/noise immunity for medium and high powered chips. When circuits in the chip's interior are connected to those near the periphery, they will be affected by this voltage instability. For these reasons, it is necessary to adopt an area array configuration for high lead count chip-to-package interconnections. Array area interconnections allow cost-effective interconnect beyond the practical limits of wire bonding. The flip chip of ball grid array as shown in FIG. 2 is well accepted as an important vehicle for providing area array interconnect.
However, even the cheapest plastic ball grid array packages are generally slightly more expensive than their quad flat tech counterparts, especially for input/output numbers below 250 or so. The cost increase at package level may turn into an overall cost decrease at board level owing to potential higher assembly yields. However, ball grid array packages involving carrier substrates with more than two layers are likely to compete with quad flat pack costs at lower pin counts. The reasons for the higher cost of plastic ball grid arrays are to be found in mainly material costs of the high temperature BT epoxy substrate and the costs of the fine line circuitry technology required.
This invention provides improvements and alternatives to prior art ball grid array assemblies and methods of making the same.